Open-Source Defiance: How US-China RISC-V Collaboration is Reshaping the Global Semiconductor Map

Latar Belakang & Kisah Di Sebalik Berita Ini

Apabila kita meneliti laporan antarabangsa mengenai industri semikonduktor, tajuk utama sering kali didominasi oleh perang tarif, sekatan teknologi mikrocip canggih, dan persaingan geopolitik yang sengit antara Amerika Syarikat (AS) dan China. Ramai pihak beranggapan bahawa dunia teknologi kini telah terbelah dua dan terputus komunikasi sepenuhnya. Namun, hakikat di sebalik tabir kejuruteraan cip sebenar memperlihatkan dinamika yang jauh lebih pragmatik dan menarik.

MIPS—sebuah nama legenda dalam reka bentuk cip dari Amerika Syarikat yang kini dimiliki oleh gergasi faundri GlobalFoundries—dilaporkan sedang memperkukuh kerjasama teknikal bersama syarikat teknologi dan institut penyelidikan di China pada skala yang belum pernah berlaku sebelum ini. Titik temu yang menghubungkan kedua-dua pihak ini ialah RISC-V, sebuah seni bina set arahan cip berasaskan sumber terbuka (open-source). Di sebalik ketegangan diplomatik, jurutera perkakasan di kedua-dua benua terus berganding bahu membina pemproses generasi masa hadapan.

Analisis Mendalam & Cara Teknologi Ini Berfungsi

Bagi memahami keunikan RISC-V, kita boleh menggunakan analogi resipi masakan.

Seni bina cip konvensional seperti x86 (yang digunakan oleh Intel dan AMD dalam komputer riba dan pelayan) atau ARM (yang menjana sebahagian besar cip telefon pintar) berfungsi seperti resipi eksklusif milik restoran mewah berfrancais. Sekiranya sesebuah syarikat mahu menghasilkan atau mengubah suai hidangan berasaskan seni bina tersebut, mereka perlu membayar fi pelesenan yang amat tinggi serta tertakluk kepada kawalan ketat pemilik hak cipta. Sebarang sekatan perdagangan atau perubahan dasar luar negara boleh melumpuhkan operasi pengeluaran cip secara serta-merta.

Sebaliknya, RISC-V ibarat buku resipi asas yang dibuka secara bebas dan neutral kepada komuniti global. Ditadbir oleh badan antarabangsa bebas yang berpangkalan di Switzerland (RISC-V International), seni bina ini kebal daripada kawalan bidang kuasa politik sesebuah negara tunggal.

Di sinilah syarikat perintis seperti MIPS memainkan peranan penting. MIPS memanfaatkan kepakaran berdekad lamanya dalam teknologi pemprosesan berprestasi tinggi dan pemprosesan berbilang benang (multi-threading). Dengan mengintegrasikan teknologi pemecut proprietari mereka ke atas rangka kerja asas RISC-V, mereka membantu pasukan jurutera di China mereka bentuk cip tersuai (System-on-Chip) yang pantas, cekap tenaga, dan kalis sekatan pelesenan konvensional.

Contoh Penggunaan Sebenar & Aplikasi Praktikal

Aplikasi cip berasaskan RISC-V kini bukan lagi sekadar eksperimen makmal, sebaliknya telah mula menggerakkan peranti dan infrastruktur utama:

1. Kenderaan Elektrik (EV) & Mobiliti Pintar: Kereta generasi baharu memerlukan ratusan Unit Kawalan Elektronik (ECU) untuk mengendalikan sistem bantuan pemandu (ADAS) dan pemprosesan penderia masa nyata. Teras mikrocip RISC-V berbilang benang mampu mengurangkan pendam masa (latency) pemprosesan sehingga lebih 25% sambil mematuhi piawaian keselamatan fungsi automotif ISO 26262.
2. Peranti Pintar & AI Pinggir (Edge AI): Kamera pengawasan pintar dan peranti IoT kini mula mengintegrasikan modul RISC-V bagi melaksanakan inferens kecerdasan buatan secara terus pada peranti tanpa perlu bergantung kepada pelayan awan.
3. Pusat Data & Pengkomputeran Awan: Pemproses pemecut vektor berasaskan RISC-V mula dipadankan bersama pelayan arus perdana untuk mempercepatkan rutin pemprosesan data intensif, seperti pengekodan video dan model bahasa raya (LLM), dengan kecekapan kuasa yang jauh lebih optimum.

Impak Kepada Pengguna & Ekosistem Industri di Malaysia

Perkembangan ini membawa implikasi strategik yang sangat signifikan kepada ekosistem teknologi Malaysia. Sebagai hab global penting dalam sektor pemasangan dan pengujian semikonduktor (OSAT) serta industri reka bentuk litar bersepadu (IC Design) yang sedang pesat dibangunkan di Selangor dan Pulau Pinang, Malaysia berada pada posisi yang amat berfaedah.

Nasihat Strategik untuk Jurutera & Syarikat Tempatan:

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Executive Industry Context & Background

The global semiconductor landscape is widely perceived through the binary lens of geopolitical confrontation. Over the past several years, stringent export controls, tariff escalations, and national security mandates issued by Washington have sought to curtail Beijing's access to leading-edge manufacturing equipment and proprietary chip architectures. In public discourse, the supply chain is portrayed as fracturing into two isolated spheres. Yet beneath the geopolitical surface, a remarkable counter-current is accelerating: cross-border collaboration centered on the open-source RISC-V instruction set architecture (ISA).

Highlighting this dynamic is the strategic posture of MIPS, a venerable American semiconductor intellectual property (IP) pioneer now under the ownership of US foundry giant GlobalFoundries. Rather than retreating from the Chinese ecosystem, MIPS has intensified its technical engagements with Chinese enterprise partners, research institutes, and fabless designers. This partnership underscores a critical reality of modern silicon engineering: open standards transcend political borders. Because RISC-V is governed by an international body based in Switzerland (RISC-V International) and is fundamentally free from single-nation jurisdiction, it represents a neutral platform where Western IP providers and Asian design houses can co-develop next-generation architectures.

Deep Architectural Breakdown & Core Engineering

To understand the magnitude of this collaborative momentum, one must look at the architectural mechanics of RISC-V compared to proprietary incumbents like x86 (Intel, AMD) and ARM. Traditional ISAs are closed ecosystems; utilizing ARM's core microarchitecture requires costly upfront licensing fees and rigid compliance structures, while x86 is strictly controlled by an American duopoly. If trade sanctions restrict access to licensing or updates, affected companies face immediate operational bottlenecks.

In contrast, RISC-V operates like the Linux of silicon. It provides a lean, modular base instruction set—consisting of fewer than 50 foundational instructions—surrounded by standard modular extensions for integer multiplication, floating-point arithmetic, atomic operations, and vector processing. Companies like MIPS bring decades of multi-threading, high-performance cache coherency, and real-time processing IP to the table. By synthesizing their proprietary silicon acceleration techniques with the open RISC-V standard, MIPS enables Chinese engineering teams to construct custom System-on-Chips (SoCs) tailored for edge-AI inferencing, automotive microcontrollers, and cloud storage accelerators without violating unilateral export bans on proprietary microarchitectures.

This engineering symbiosis is mutually beneficial. Western IP vendors gain immediate access to high-volume commercial testbeds and rapid tape-out cycles in China, while Chinese designers obtain proven architectural building blocks to validate their custom silicon in foundries across the globe.

Real-World Applications & Benchmark Performance

The tangible outcomes of this cross-border integration are already evident across multiple industrial sectors. In automotive electronics, modern electric vehicles (EVs) require hundreds of Electronic Control Units (ECUs) alongside powerful domain controllers for advanced driver-assistance systems (ADAS). Traditional legacy microcontroller IP often introduces latency bottlenecks and high power draw. Through MIPS-driven multi-threaded RISC-V cores, automotive silicon developers have demonstrated real-time compute latency reductions exceeding 25% while maintaining strict ISO 26262 functional safety compliance.

In hyperscale cloud data centers and edge infrastructure, custom RISC-V vector acceleration units are being deployed alongside conventional server processors to handle specialized workloads such as real-time video transcoding, network packet filtering, and large language model (LLM) quantization. In benchmarking matrix multiplication and tensor processing routines, optimized 64-bit RISC-V cluster engines achieve energy efficiency figures (TOPS/Watt) comparable to dedicated commercial DSPs, all while running lightweight embedded Linux and standard open toolchains like GCC and LLVM.

Strategic Market Outlook & Key Takeaways

The deepening ties between US IP innovators and Chinese semiconductor ecosystems reveal the limits of technological isolationism. When knowledge is decentralized and rooted in open standards, commercial pragmatism and engineering efficiency frequently outpace regulatory restrictions.

Looking forward, the semiconductor industry is moving toward a hybrid paradigm. Proprietary architectures will continue to dominate legacy personal computing and enterprise servers, but the hyper-growth sectors—autonomous mobility, edge artificial intelligence, IoT, and custom cloud silicon—are gravitating rapidly toward RISC-V. For global tech leaders and semiconductor executives, the takeaway is unequivocal: participating actively in open architectural consortia is no longer just a cost-saving measure; it is an essential strategic hedge against supply chain balkanization and geopolitical disruption.

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